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This page provides draft copies of papers and other material relating  to selected research and educational publications. Further details of the educational PLL test course and simulation files are provided on other pages on this site.  My key research papers have focused towards indirect measurement techniques for phase noise / jitter detection.  I am currently trying to forward this work on my own and am interested in any collaboration / funding etc in this area. I have further publications and examples relating to this work. Please contact me directly if you require any more information.

This paper explains the motivations for development of  a basic PLL training course. The course consists of a set of simulations files and corresponding hardware. Simulation files were used to allow the student to gain familiarity with the material prior to attending the practical lab sessions.

This paper describes research based upon investigation of jitter / phase noise mechanisms in Charge-Pump based frequency synthesis systems. The research was interesting but is still open ended. If anyone is interested in collaboration related to this work please contact me.

This paper was presented at the 2nd IEEE IC test workshop, Limerick 2004.This paper describes very preliminary investigations into frequency counting techniques to identify supply coupling faults in CP-PLLs.

This paper is explains collaborative work with the University of Limerick .The work involved adaptation of the PLL training course for web based delivery of the hardware based lab session.

Phase locked loop System Design and Measurement Tutorial Consisting of Physical Hardware and Co-Simulation Environment

Simple frequency counting techniques for Analysis of VCO / CP-PLL coupled noise sensitivity in fully embedded CP-PLLs.

Detection and evaluation of deterministic jitter cases in charge pump phase locked loops and pre-detection using simple methods

Development of a Remote Access Facility for a PLL Test Course

Selected Publications.

Educational based hardware, simulation, and remote access adaptation

Indirect methods for estimating phase noise and jitter in CP-PLL’s and basic CP-PLL design for test techniques.

E-mail: martin_at_mjb-rfelectronics-synthesis_dot_com

For more information:

MJBRF-Electronics

Dr. Martin John Burbidge

Electronics and RF, research, development and prototyping.